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? semiconductor components industries, llc, 2002 june, 2002 rev. 1 1 publication order number: mc74lvx393/d mc74lvx393 product preview dual 4-bit binary ripple counter the mc74lvx393 is an advanced high speed cmos dual 4bit binary ripple counter fabricated with silicon gate cmos technology. it achieves high speed operation similar to equivalent bipolar schottky ttl while maintaining cmos low power dissipation. this device consists of two independent 4bit binary ripple counters with parallel outputs from each counter stage. a 256 counter can be obtained by cascading the two binary counters. internal flipflops are triggered by hightolow transitions of the clock input. reset for the counters is asynchronous and activehigh. state changes of the q outputs do not occur simultaneously because of internal ripple delays. therefore, decoded output signals are subject to decoding spikes and should not be used as clocks or as strobes except when gated with the clock of the lvx393. the inputs tolerate voltages up to 7 v, allowing the interface of 5 v systems to 3 v systems. ? high speed: f max = 90 mhz (typ) at v cc ? low power dissipation: i cc = 4 a (max) at t a = 25 c ? high noise immunity: v nih = v nil = 28% v cc ? power down protection provided on inputs ? balanced propagation delays ? designed for 2 v to 3.6 v operating range ? low noise: v olp = 0.8 v (max) ? pin and function compatible with other standard logic families ? latchup performance exceeds 300 ma ? chip complexity: 236 fets this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. marking diagrams ordering information a = assembly location l, wl = wafer lot y = year w, ww = work week soic14 d suffix case 751a tssop14 dt suffix case 948g soic eiaj14 m suffix case 965 1 7 8 14 8 14 7 1 1 14 8 7 lvx393 awlyww lvx 393 awlyww lvx393 alyw device package shipping mc74lvx393m soic eiaj16 50 units/rail mc74lvx393mel soic eiaj16 2000 units/reel http://onsemi.com
mc74lvx393 http://onsemi.com 2 11 12 13 14 8 9 10 5 4 3 2 1 7 6 2qb 2qa rd2 v cc 2qd 2qc 1qb 1qa rd1 cp1 gnd 1qc 1qd figure 1. pin assignment function table inputs clock reset outputs xh l h l no change l l no change l no change l next state figure 2. logic diagram nqa nqb nqc nqd cpn rdn 1, 13 2, 12 3, 11 4, 10 5, 9 6, 8 binary counter figure 3. iec logic symbol 3 1qa 1qb 1qc 1qd 2qa 2qb 2qc 2qd 4 5 6 11 10 9 8 13 12 2 1 rd1 + ctriv 16 0 3 ct cp1 rd2 cp2 ct = 0 qa qb qc qd cp rd 1, 13 2, 12 3, 11 4, 10 5, 9 6, 8 figure 4. expanded logic diagram c dq q c dq q c dq q c dq q
mc74lvx393 http://onsemi.com 3 maximum ratings symbol parameter value unit v cc dc supply voltage 0.5 to 7.0 v v in dc input voltage 0.5 to 7.0 v v out dc output voltage 0.5 to v cc 0.5 v i ik dc input diode current v i < gnd 20 ma i ok dc output diode current v o < gnd 20 ma i out dc output sink current 25 ma i cc dc supply current per supply pin 75 ma t stg storage temperature range 65 to 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias 150 c ja thermal resistance (note 1) soic tssop 125 170 c/w msl moisture sensitivity level 1 f r flammability rating oxygen index: 30% 35% ul94vo (0.125 in) v esd esd withstand voltage human body model (note 2) machine model (note 3) charged device model (note 4) > 2000 > 200 n/a v i latchup latchup performance above v cc and below gnd at 85 c (note 5) 300 ma maximum ratings are those values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolutemaximumrated conditions is not implied. functional operation should be restricted to the recommended operating conditions. 1. measured with minimum pad spacing on an fr4 board, using 10 mmby1 inch, 2ounce copper trace with no air flow. 2. tested to eia/jesd22a114a. 3. tested to eia/jesd22a115a. 4. tested to jesd22c101a. 5. tested to eia/jesd78. recommended operating conditions symbol parameter min max unit v cc supply voltage 2.0 3.6 v v i input voltage (note 6) 0 5.5 v v o output voltage (high or low state) 0 5.5 v t a operating freeair temperature 40 125 c t/ v input transition rise or fall rate v cc = 3.0 v 0.3 v 0 100 ns/v 6. unused inputs may not be left open. all inputs must be tied to a high or lowlogic input voltage level. note: the ja of the package is equal to 1/derating. higher junction temperatures may affect the expected lifetime of the device per the tab le and figure below. device junction temperature versus time to 0.1% bond failures junction temperature c time, hours time, years 80 1,032,200 117.8 90 419,300 47.9 100 178,700 20.4 110 79,600 9.4 120 37,000 4.2 130 17,800 2.0 140 8,900 1.0 1 1 10 100 1000 failure rate of plastic = ceramic until intermetallics occur figure 5. failure rate vs. time junction temperature normalized failure rate time, years t j = 130 c t j = 120 c t j = 110 c t j = 100 c t j = 90 c t j = 80 c
mc74lvx393 http://onsemi.com 4 dc electrical characteristics v cc t a = 25 c 40 c t a 85 c t a 125 c symbol parameter condition (v) min typ max min max min max unit v ih highlevel input voltage 2.0 to 5.5 0.72 v cc 0.72 v cc 0.72 v cc v v il lowlevel input voltage 2.0 to 5.5 0.28 v c c 0.28 v cc 0.28 v cc v v oh highlevel output voltage i oh =50 a 2.0 to 5.5 v cc 0.1 v cc v cc 0.1 v v in =v il or v ih i oh =4ma 2.3 1.9 2.1 1.9 i oh =8ma 2.7 2.2 2.4 2.2 v ol lowlevel output voltage i ol =50 a 2.0 to 5.5 0.1 0.1 v v in =v il or v ih i ol =4ma 3.0 0.36 0.44 i ol =8ma 4.5 0.36 0.44 i ol =16ma 3.0 0.28 0.4 0.4 i ol =24ma 3.0 0.38 0.55 0.55 i ol =32ma 4.5 0.42 0.55 0.55 i in input leakage current v in = v cc or gnd 0to 5.5 0.1 1.0 a i off power offoutput leakage current v out = 5.5 v 0 1 10 a i cc quiescent supply current v in = v cc or gnd 5.5 1 10 a
mc74lvx393 http://onsemi.com 5 ac electrical characteristics (input t r = t f = 3.0 ns) t a = 25 c t a 85 c t a 125 c symbol parameter test conditions min typ max min max min max unit ???? ? ?? ? ???? f max ??????? ? ????? ? ??????? maximum clock frequency (50% duty cycle) ????????? ? ??????? ? ????????? v cc = 3.3 0.3 v c l = 15 pf c l = 50 pf ??? ? ? ? ??? 75 45 ??? ? ? ? ??? 120 65 ??? ? ? ? ??? ??? ? ? ? ??? 65 35 ??? ? ? ? ??? ??? ? ? ? ??? 65 35 ??? ? ? ? ??? ?? ?? ?? mhz ???? ???? ??????? ??????? ????????? ????????? v cc = 5.0 0.5 v c l = 15 pf c l = 50 pf ??? ??? 125 85 ??? ??? 170 115 ??? ??? ??? ??? 105 75 ??? ??? ??? ??? 105 75 ??? ??? ?? ?? ???? ? ?? ? ???? t plh , t phl ??????? ? ????? ? ??????? maximum propagation delay, cp to qa ????????? ? ??????? ? ????????? v cc = 3.3 0.3 v c l = 15 pf c l = 50 pf ??? ? ? ? ??? ??? ? ? ? ??? 8.6 11.1 ??? ? ? ? ??? 13.2 16.7 ??? ? ? ? ??? 1.0 1.0 ??? ? ? ? ??? 15.5 19.0 ??? ? ? ? ??? 1.0 1.0 ??? ? ? ? ??? 15.5 19.0 ?? ?? ?? ns ???? ? ?? ? ???? ??????? ? ????? ? ??????? ????????? ? ??????? ? ????????? v cc = 5.0 0.5 v c l = 15 pf c l = 50 pf ??? ? ? ? ??? ??? ? ? ? ??? 5.8 7.3 ??? ? ? ? ??? 8.5 10.5 ??? ? ? ? ??? 1.0 1.0 ??? ? ? ? ??? 10.0 12.0 ??? ? ? ? ??? 1.0 1.0 ??? ? ? ? ??? 10.0 12.0 ?? ?? ?? ???? ???? t plh , t phl ??????? ??????? maximum propagation delay, cp to qb ????????? ????????? v cc = 3.3 0.3 v c l = 15 pf c l = 50 pf ??? ??? ??? ??? 10.2 12.7 ??? ??? 15.8 19.3 ??? ??? 1.0 1.0 ??? ??? 18.5 22.0 ??? ??? 1.0 1.0 ??? ??? 18.5 22.0 ?? ?? ns ???? ? ?? ? ???? ??????? ? ????? ? ??????? ????????? ? ??????? ? ????????? v cc = 5.0 0.5 v c l = 15 pf c l = 50 pf ??? ? ? ? ??? ??? ? ? ? ??? 6.8 8.3 ??? ? ? ? ??? 9.8 11.8 ??? ? ? ? ??? 1.0 1.0 ??? ? ? ? ??? 11.5 13.5 ??? ? ? ? ??? 1.0 1.0 ??? ? ? ? ??? 11.5 13.5 ?? ?? ?? ???? ???? t plh , t phl ??????? ??????? maximum propagation delay, cp to qc ????????? ????????? v cc = 3.3 0.3 v c l = 15 pf c l = 50 pf ??? ??? ??? ??? 11.7 14.2 ??? ??? 18.0 21.5 ??? ??? 1.0 1.0 ??? ??? 21.0 24.5 ??? ??? 1.0 1.0 ??? ??? 21.0 24.5 ?? ?? ns ???? ? ?? ? ???? ??????? ? ????? ? ??????? ????????? ? ??????? ? ????????? v cc = 5.0 0.5 v c l = 15 pf c l = 50 pf ??? ? ? ? ??? ??? ? ? ? ??? 7.7 9.2 ??? ? ? ? ??? 11.2 13.2 ??? ? ? ? ??? 1.0 1.0 ??? ? ? ? ??? 13.0 15.0 ??? ? ? ? ??? 1.0 1.0 ??? ? ? ? ??? 13.0 15.0 ?? ?? ?? ???? ? ?? ? ???? t plh , t phl ??????? ? ????? ? ??????? maximum propagation delay, cp to qd ????????? ? ??????? ? ????????? v cc = 3.3 0.3 v c l = 15 pf c l = 50 pf ??? ? ? ? ??? ??? ? ? ? ??? 13.0 15.5 ??? ? ? ? ??? 19.7 23.2 ??? ? ? ? ??? 1.0 1.0 ??? ? ? ? ??? 23.0 26.5 ??? ? ? ? ??? 1.0 1.0 ??? ? ? ? ??? 23.0 26.5 ?? ?? ?? ns ???? ???? ??????? ??????? ????????? ????????? v cc = 5.0 0.5 v c l = 15 pf c l = 50 pf ??? ??? ??? ??? 8.5 10.0 ??? ??? 12.5 14.5 ??? ??? 1.0 1.0 ??? ??? 14.5 16.5 ??? ??? 1.0 1.0 ??? ??? 14.5 16.5 ?? ?? ???? ? ?? ? ???? t phl ??????? ? ????? ? ??????? maximum propagation delay, rd to qn ????????? ? ??????? ? ????????? v cc = 3.3 0.3 v c l = 15 pf c l = 50 pf ??? ? ? ? ??? ??? ? ? ? ??? 7.9 10.4 ??? ? ? ? ??? 12.3 15.8 ??? ? ? ? ??? 1.0 1.0 ??? ? ? ? ??? 14.5 18.0 ??? ? ? ? ??? 1.0 1.0 ??? ? ? ? ??? 14.5 18.0 ?? ?? ?? ns ???? ? ?? ? ???? ??????? ? ????? ? ??????? ????????? ? ??????? ? ????????? v cc = 5.0 0.5 v c l = 15 pf c l = 50 pf ??? ? ? ? ??? ??? ? ? ? ??? 5.4 6.9 ??? ? ? ? ??? 8.1 10.1 ??? ? ? ? ??? 1.0 1.0 ??? ? ? ? ??? 9.5 11.5 ??? ? ? ? ??? 1.0 1.0 ??? ? ? ? ??? 9.5 11.5 ?? ?? ?? ???? ???? t oslh , t ??????? ??????? output to output skew ????????? ????????? v cc = 3.3 0.3 v c l = 50 pf ??? ??? ??? ??? ??? ??? 1.5 ??? ??? ??? ??? 1.5 ??? ??? ??? ??? 1.5 ?? ?? pf ???? ???? t oshl ??????? ??????? (note 7) ????????? ????????? v cc = 5.0 0.5 v c l = 50 pf ??? ??? ??? ??? ??? ??? 1.0 ??? ??? ??? ??? 1.0 ??? ??? ??? ??? 1.0 ?? ?? ???? ???? c in ??????? ??????? maximum input capacitance ????????? ????????? ??? ??? ??? ??? 4 ??? ??? 10 ??? ??? ??? ??? 10 ??? ??? ??? ??? 10 ?? ?? pf typical @ 25 c, v cc = 5.0 v c pd power dissipation capacitance (note 8) 23 pf 7. parameter guaranteed by design. t oslh = |t plhm t plhn |, t oshl = |t phlm t phln |. 8. c pd is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption with out load. average operating current can be obtained by the equation: i cc(opr ) = c pd v cc f in + i cc . c pd is used to determine the noload dynamic power consumption; p d = c pd v cc 2 f in + i cc v cc . noise characteristics (input t r = t f = 3.0 ns, c l = 50 pf, v cc = 5.0 v) t a = 25 c symbol parameter typ max unit v olp quiet output maximum dynamic v ol 0.5 0.8 v v olv quiet output minimum dynamic v ol 0.5 0.8 v v ihd minimum high level dynamic input voltage 3.5 v v ild maximum low level dynamic input voltage 1.5 v
mc74lvx393 http://onsemi.com 6 timing requirements (input t r = t f = 3.0 ns) t a = 25 c t a 85 c t a 125 c symbol parameter test conditions typ limit limit limit unit t w minimum pulse width, cp v cc = 3.3 0.3 v v cc = 5.0 0.5 v 5.0 5.0 5.0 5.0 5.0 5.0 ns t w minimum pulse width, rd v cc = 3.3 0.3 v v cc = 5.0 0.5 v 5.0 5.0 5.0 5.0 5.0 5.0 ns t rec minimum recovery time, rd to cp v cc = 3.3 0.3 v v cc = 5.0 0.5 v 5.0 4.0 5.0 4.0 5.0 4.0 ns t r , t f minimum input rise and fall times v cc = 3.3 0.3 v v cc = 5.0 0.5 v 330 100 330 100 330 100 ns t phl v cc gnd v cc gnd 50% 50% v cc 50% t rec cp qn rd figure 6. switching waveforms cp qn 50% v cc gnd t w 1/f max t plh t phl 50% v cc t w figure 7. test circuit *includes all probe and jig capacitance c l * test point device under test output
mc74lvx393 http://onsemi.com 7 01234567891011121314150 cp rd qa qb qc qd figure 8. timing diagram count sequence outputs count qd qc qb qa 0 l l l l 1 l l l h 2 l l h l 3 l l h h 4 l h l l 5 l h l h 6 l h h l 7 l h h h 8 h l l l 9 h l l h 10 h l h l 11 h l h h 12 h h l l 13 h h l h 14 h h h l 15 h h h h
mc74lvx393 http://onsemi.com 8 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t t f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019 soic14 d suffix case 751a03 issue f
mc74lvx393 http://onsemi.com 9 package dimensions dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l u seating plane 0.10 (0.004) t ??? ??? ??? section nn detail e j j1 k k1 detail e f m w 0.25 (0.010) 8 14 7 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t v 14x ref k n n tssop dt suffix case 948g01 issue o
mc74lvx393 http://onsemi.com 10 package dimensions h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 1.42 --- 0.056 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). 0.13 (0.005) m 0.10 (0.004) d z e 1 14 8 7 e a b view p c l detail p m a b c d e e 0.50 m z so14 m suffix case 96501 issue o
mc74lvx393 http://onsemi.com 11 notes
mc74lvx393 http://onsemi.com 12 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc74lvx393/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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